1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to a driving circuit for a liquid crystal display device and a method of driving a liquid crystal display device.
2. Discussion of the Related Art
In general, liquid crystal display (LCD) devices include two substrates disposed such that respective electrodes of the two substrates face each other and a liquid crystal layer is interposed between the respective electrodes. Accordingly, when a voltage is applied to the electrodes, an electric field is induced to the liquid crystal layer to modulate a light transmittance of the liquid crystal layer. Thus, by reorienting liquid crystal molecules of the liquid crystal layer, images are displayed.
FIG. 1 is a schematic view of a liquid crystal display device according to the related art. In FIG. 1, a liquid crystal display device includes a liquid crystal panel 2, a gate driver 6, a data driver 4, and a gamma voltage generator 8. The liquid crystal panel 2 includes a plurality of gate lines GL1-GLm and a plurality of data lines DL1-DLn. A pixel region P is defined by the plurality of gate lines GL1-GLm and the plurality of data lines DL1-DLn, and is disposed in matrix configuration on the liquid crystal panel 2. In addition, a thin film transistor (TFT) of a switching element is connected to the plurality of gate lines GL1-GLm and the plurality of data lines DL1-DLn. The gate driver 6 and the data driver 4 are connected to the plurality of gate lines GL1-GLm and the plurality of data lines DL1-DLn, respectively. The gate driver 6 sequentially supplies the plurality of gate lines GL1-GLm with scan signals and drives the TFT connected to the plurality of gate lines GL1-GLm. The gamma voltage generator 8 is connected to the data driver 4 and supplies the data driver 4 with gamma voltage, as shown in FIG. 2, using a source voltage VDD.
FIG. 2 is a schematic view of gamma voltages of a gamma voltage generator for a liquid crystal display device according to the related art. In FIG. 2, a gamma voltage generator 8 (in FIG. 1) generates a gamma voltage Vγ having several DC (direct current) levels V0, . . . , Vn−1, Vn, and VDD according to a brightness of video signals. The gamma voltage Vγ is supplied to the plurality of data lines DL1-DLn.
FIG. 3 is a schematic equivalent circuit diagram of a pixel region of a liquid crystal display device according to the related art. In FIG. 3, a pixel region includes a gate line GL, a data line DL, a common line CL, a thin film transistor (TFT) connected to the gate line GL and the data line DL, and a liquid crystal capacitor Clc is connected to the TFT and the common line CL. In addition, a parasitic capacitor Cgs is created between the gate line GL and a source electrode of the TFT, and a parasitic resistor Rftf is created between the drain electrode and the source electrode of the TFT. The parasitic resistor Rtft, which is an equivalent resistor generated between the drain electrode and the source electrode of the TFT while the TFT is turned OFF, does not have a fixed value. The gamma voltage Vγ (in FIG. 2) and a common voltage Vcom are applied to the liquid crystal capacitor Clc through the data line DL and the common line CL, respectively, when the TFT is turned ON. The parasitic capacitor Cgs is charged by the difference between a gate voltage and the gamma voltage Vγ (in FIG. 2) while the TFT is turned ON, i.e., a scan signal has a high value. Conversely, the parasitic capacitor Cgs is discharged while the TFT is turned OFF, i.e., the scan signal has a low value. Charges from the parasitic capacitor Cgs may be input to the liquid crystal capacitor Clc and may influence the voltage of the liquid crystal capacitor Clc. If the gamma voltage Vγ (in FIG. 2), the scan signal, and the common voltage Vcom vary with the same values for every pixel region, a sum of charges input to the parasitic resistor Rftf and the liquid crystal capacitor Clc from the parasitic capacitor Cgs may be kept constant independent of a position of the pixel region.
When the LCD device is a polycrystalline silicon TFT, the data driver 4 (in FIG. 1) may be formed in the liquid crystal panel 2 (in FIG. 1). In addition, a digital-to-analog converter (DAC) may be formed in the data driver (in FIG. 1) as a digital circuit.
FIG. 4 is a schematic circuit diagram of a RAMP-type digital-to-analog converter for a liquid crystal display device according to the related art. In FIG. 4, a RAMP signal generator 10 is implemented outside of a liquid crystal panel 2 (in FIG. 1), and a pulse width modulator (PWM) 12 and a switch 15 are implemented in the liquid crystal panel 2 (in FIG. 1). The PWM 12 generates PWM pulses having different pulse widths corresponding to gray levels of video signals, and the switch 15, such as a field effect transistor, is controlled by the PWM pulses. A DC level of a gamma voltage Vγ (in FIG. 2) is determined by the pulse width of the PWM pulse generated by the PWM 12. In addition, the gamma voltage Vγ (in FIG. 2) is supplied to a data capacitor C through one of the plurality of data lines DL1-DLn. The data capacitor C is equivalent to a total capacitance connected to each of the plurality of data lines DL1-DLn.
FIG. 5 is a schematic timing chart of a RAMP-type digital-to-analog converter for a liquid crystal display device according to the related art. In FIG. 5, a RAMP signal of a RAMP signal generator 10 (in FIG. 4) has an inclined portion that corresponds to all gray levels, and is periodically supplied to a switch 15 (in FIG. 4) for one horizontal sync time period. A pulse width modulator (PWM) 12 (in FIG. 4) generates a PWM pulse to adjust a turn-ON time of the switch 15 (in FIG. 4), and a DC level of a gamma voltage Vγ (in FIG. 2) is determined by the pulse width of the PWM pulse. The gamma voltage Vγ (in FIG. 2) is supplied to a data capacitor C through a plurality of data lines DL1-DLn, and images are produced having a gray level corresponding to the gamma voltage Vγ (in FIG. 2).
Since the DAC shown in FIG. 4 is implemented with digital circuits, the DAC is not susceptible to non-uniform operational characteristics of the TFTs in the liquid crystal panel 2 (in FIG. 1). Accordingly, it is simple to obtain optimum gamma correction through waveform adjustment of the RAMP signal. However, since an external RAMP signal generator 10 (in FIG. 4) is used, the DAC has a large output load. Moreover, the output load greatly varies according to the gray level. Accordingly, power consumption increases in the external RAMP signal generator 10 (in FIG. 4).